Toshihiro Hanawa

Papers written in English

Journal papers

  1. Takahiro Suzuki, et al., "Demonstration of 10-Gbps Real-time Reed-Solomon Decoding Using GPU Direct Transfer and Kernel Scheduling for Flexible Access Systems," IEEE/OSA Journal of Lightwave Technology, Vol. 36, Issue 10, pp. 1875-1881, 2018. doi: http://doi.org/10.1109/JLT.2018.2793938
     
  2. K. Matsumoto, N. Fujita, T. Hanawa, and T. Boku, "Implementation and Evaluation of NAS Parallel CG Benchmark on GPU Cluster with Proprietary Interconnect TCA," Lecture Notes in Computer Science (LNCS) 10150, pp. 135--145, 2017. DOI: http://dx.doi.org/10.1007/978-3-319-61982-8_14
     
  3. Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Toshihiro Hanawa, Shin'ichi Miura, Taisuke Boku, "Peach: A Multicore Communication System on Chip with PCI Express," IEEE Micro, Vol. 31, No. 6, pp. 39-50, 2011. doi: http://doi.ieeecomputersociety.org/10.1109/MM.2011.93
     
  4. Soichiro Ikuno, Toshihiro Hanawa, Teruou Takayama, and Atsushi Kamitani, "Evaluation of Parallelized Meshless Approach: Application to Shielding Current Analysis in HTS," IEEE Transactions on Magnetics, Vol. 44, Issue 6, pp. 1230-1233, May. 2008. doi: http://dx.doi.org/10.1109/TMAG.2007.914872
     
  5. Toshihiro Hanawa and Soichiro Ikuno, "Large-Scale Simulation for Optical Propagation in 3-D Photonic Crystal Using the FDTD Method With Parallel Processing," IEEE Transactions on Magnetics, Vol. 43, Issue 4, pp. 1545-1548, Apr. 2007. doi: http://dx.doi.org/10.1109/TMAG.2007.892462
     
  6. Toshihiro Hanawa and Soichiro Ikuno, "Numerical Simulation of Electromagnetic Field by Parallelized 3-D AIBO-FDTD," Journal of Plasma Physics, Volume 72, Issue 06, pp. 1053-1056, Dec. 2006. doi: http://dx.doi.org/10.1017/S0022377806005216
     
  7. Toshihiro Hanawa, Masatoshi Kurosawa, and Soichiro Ikuno, "Investigation on 3-D implicit FDTD method for parallel processing," IEEE Transactions on Magnetics, Volume 41, Issue 5, pp. 1696-1699, May 2005. doi: http://dx.doi.org/10.1109/TMAG.2005.846066
     
  8. Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa, and Hideharu Amano, "The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism)," Parallel Computing, Vol. 31, Issues 3-4, pp. 352-370, Mar. 2005. doi: http://dx.doi.org/10.1016/j.parco.2004.11.004
     
  9. Toshihiro Hanawa, Soichiro Ikuno, and Atsushi Kamitani, "Application of parallelized multigrid method to solution of MHD equilibrium with MPI," IEEE Transactions on Magnetics, Volume 40, Issue 2, Part 2, pp. 1005--1008, Mar. 2004. doi:http://dx.doi.org/10.1109/TMAG.2004.825440
     
  10. Junji Yamamoto, Takashi Fujiwara, Takuji Komeda, Takayuki Kamei, Toshihiro Hanawa, and Hideharu Amano, "Performance evaluation of SNAIL: A multiprocessor based on the Simple Serial Synchronized," Parallel Computing, Vol. 25, No. 9, pp. 1081-1103, Sep. 1999. doi: http://dx.doi.org/10.1016/S0167-8191(99)00038-1
     
  11. Toshihiro Hanawa, Takayuki Kamei, Hideki Yasukawa, Katsunobu Nishimura, and Hideharu Amano, "MINC: Multistage Interconnection Network with Cache control mechanism," IEICE Transactions on Information and Systems, Vol. E80-D, No. 9, pp. 863-870, Sep. 1997.
     
  12. Akira Funahashi, Toshihiro Hanawa, and Hideharu Amano, "Fault Tolerance of the TBSF(Tandem Banyan Switching Fabrics) and PBSF(Piled Banyan Switching Fabrics)," IEICE Transactions on Information and Systems, Vol. E79-D, No. 8, pp. 1180-1189, Aug. 1996.

Conference proceedings

  1. Y. Nomura, I. Sato, T. Hanawa, S. Hanaoka, T. Nakao, T. Takenaga, D. Sato, T. Hoshino, Y. Sekiya, S. Ohshima, N. Hayashi, O. Abe, Preliminary development of training environment for deep learning on supercomputer system, 32nd International Congress and Exhibition on Computer Assisted Radiology (CARS 2018), June 2018 (accepted).
     
  2. Sangyeup Kim, Takahiro Suzuki, Jun-ichi Kani, Akihiro Otaka,Toshihiro Hanawa, "Coherent Receiver DSP Implemented on a General-Purpose Server for Full Software-Defined Optical Access," 2018 Optical Fiber Communication Conference (OFC), Mar. 2018. (Top-scored paper) DOI: https://doi.org/10.1364/OFC.2018.Tu3L.2
     
  3. Takahiro Suzuki, Sangyeup Kim, Jun-ichi Kani, Akihiro Otaka, Toshihiro Hanawa, "10-Gbps Real-time Burst-Frame Synchronization Using Dual-Stage Detection for Full-Software Optical Access Systems," 2018 Optical Fiber Communication Conference (OFC), Mar. 2018. DOI: https://doi.org/10.1364/OFC.2018.Tu3L.6
     
  4. Masashi Horikoshi, Larry Meadows, Tom Elken, Pradeep Sivakumar, Edward Mascarenhas, James Erwin, Dmitry Durnov, Alexander Sannikov, Toshihiro Hanawa and Taisuke Boku, "Scaling Collectives on Large Clusters of Intel(R) Architecture Processors," Intel eXtreme Performance User Group (IXPUG) Workshop at HPC Asia 2018, Jan. 2018. DOI: http://dx.doi.org/10.1145/3176364.3176373
     
  5. Kengo Nakajima, Toshihiro Hanawa, "Communication-Computation Overlapping with Dynamic Loop Scheduling for Preconditioned Parallel Iterative Solvers on Multicore and Manycore Clusters", Parallel Programming Models and Systems Software for High-End Computing (P2S2), in conjunction with ICPP2017, pp. 210-219, Aug. 2017. DOI: http://dx.doi.org/10.1109/ICPPW.2017.39
     
  6. Takahiro Kaneda, Ryotaro Sakai, Naoki Nishikawa, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano: Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 9 pages, Jun. 2017.
     
  7. Kenta Sato, Norihisa Fujita, Toshihiro Hanawa, Taisuke Boku, and Khaled Z. Ibrahim, "GPU-Ready GASNet Implementation on the TCA Proprietary Interconnect Architecture", Intl. Conf. on Computational Science and Computational Intelligence (CSCI) 2016, Dec. 2016. DOI: http://dx.doi.org/10.1109/CSCI.2016.0119
     
  8. T. Suzuki, S. Y. Kim, J. i. Kani, K. I. Suzuki, A. Otaka, T. Hanawa, "Parallelization of cipher algorithm on CPU/GPU for real-time software-defined access network," 2015 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA), pp. 484-487, Dec. 2015. DOI: http://dx.doi.org/10.1109/APSIPA.2015.7415318
     
  9. Toshihiro Hanawa, Hisafumi Fujii, Norihisa Fujita, Tetsuya Odajima, Kazuya Matsumoto, and Taisuke Boku, "Evaluation of FFT for GPU Cluster Using Tightly Coupled Accelerators Architecture," Workshop on Heterogeneous and Unconventional Cluster Architectures and Applications (HUCAA) 2015 in conjunction with Cluster2015, pp. 635-641, Sep. 2015. DOI: http://dx.doi.org/10.1109/CLUSTER.2015.113
     
  10. Tetsuya Odajima, Taisuke Boku, Toshihiro Hanawa, Hitoshi Murai, Masahiro Nakao, Akihiro Tabuchi, and Mitsuhisa Sato, "Hybrid Communication with TCA and InfiniBand? on A Parallel Programming Language XcalableACC for GPU Clusters," Workshop on Heterogeneous and Unconventional Cluster Architectures and Applications (HUCAA) 2015 in conjunction with Cluster2015, pp. 627-634, Sep. 2015. DOI: http://dx.doi.org/10.1109/CLUSTER.2015.112
     
  11. Toshihiro Hanawa, Hisafumi Fujii, Norihisa Fujita, Tetsuya Odajima, Kazuya Matsumoto, Yuetsu Kodama, Taisuke Boku, "Improving Strong-Scaling on GPU Cluster Based on Tightly Coupled Accelerators Architecture," IEEE Cluster 2015 (Short), pp. 88-91, Sep. 2015. DOI: http://dx.doi.org/10.1109/CLUSTER.2015.154
     
  12. Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, and Hideharu Amano, "Reduction calculator in an FPGA based switching Hub for high performance clusters," 25th International Conference on Field Programmable Logic and Applications (FPL), (poster session) pp. 1-4, Sep. 2015. DOI: http://dx.doi.org/10.1109/FPL.2015.7293985
     
  13. Takahiro Kaneda, Takuji Mitsuishi, Yuki Katsuta, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku, "Parallel processing of Breadth First Search by Tightly Coupled Accelerator," The 21st International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'15), pp. 360-366, Jul. 2015.
     
  14. Kazuya Matsumoto, Toshihiro Hanawa, Yuetsu Kodama, Hisafumi Fujii, and Taisuke Boku, ” Implementation of CG Method on GPU Cluster with Proprietary Interconnect TCA for GPU Direct Communication,” The Internatonal Workshop on Accelerators and Hybrid Exascale Systems (AsHES2015) , pp. 647-655, May, 2015. DOI: http://dx.doi.org/10.1109/IPDPSW.2015.102
     
  15. Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano, Hitoshi Murai, Masayuki Umemura, and Mitsuhisa Sato, "Towards Unification of Accelerated Computing and Interconnection for Extreme-Scale Computing", 11th International Symposium on Applied Reconfigurable Computing (ARC2015), LNCS 9040, pp. 463-474, Apr 2015 (Invited paper) doi:http://dx.doi.org/10.1007/978-3-319-16214-0_43
     
  16. Takuya Kuhara, Takahiro Kaneda, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, and Hideharu Amano, "A preliminarily evaluation of PEACH3: a switching hub for tightly coupled accelerators," 2nd International Workshop on Computer Systems and Architectures (CSA'14), in conjunction with the 2nd International Symposium on Computing and Networking (CANDAR 2014), pp. 377 - 381, Dec. 2014. doi:http://dx.doi.org/10.1109/CANDAR.2014.44
     
  17. Masahiro Nakao, Hitoshi Murai, Takenori Shimosaka, Akihiro Tabuchi, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato, "XcalableACC: Extension of XcalableMP PGAS Language using OpenACC for Accelerator Clusters," Workshop on accelerator programming using directives (WACCPD 2014), in conjunction with SC14, pp. 27-36, Nov. 2014. doi:http://doi.ieeecomputersociety.org/10.1109/WACCPD.2014.6
     
  18. Norihisa Fujita, Hisafumi Fujii, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Yoshinobu Kuramashi, and Mike Clark, "QCD Library for GPU Cluster with Proprietary Interconnect for GPU Direct Communication," 12th International Workshop Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar2014), in conjunction with EuroPAR2014, Lecture Notes in Computer Science Volume 8805, pp. 251-262, Aug. 2014. doi:http://dx.doi.org/10.1007/978-3-319-14325-5_22
     
  19. Yuetsu Kodama, Toshihiro Hanawa, Taisuke Boku and Mitsuhisa Sato, "PEACH2: FPGA based PCIe network device for Tightly Coupled Accelerators," Fifth International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2014), pp. 3-8, Jun. 2014. doi: http://dx.doi.org/10.1145/2693714.2693716[Best Paper Award]
     
  20. Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, and Taisuke Boku: Task Level Pipelining on Multiple Accelerators via FPGA Switch, the 12th IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN2014), Track 811-026, Feb 2014. doi: http://dx.doi.org/10.2316/P.2014.811-026
     
  21. Tetsuya Odajima, Taisuke Boku, Mitsuhisa Sato, Toshihiro Hanawa, Yuetsu Kodama, Raymond Namyst, Samuel Thibault, Olivier Aumage, "Adaptive Task Size Control on High Level Programming for GPU/CPU Work Sharing," 13th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP 2013), Lecture Notes in Computer Science Volume 8286, pp. 59-68, Dec. 2013. doi: http://dx.doi.org/10.1007/978-3-319-03889-6_7
     
  22. Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku, "Task level pipelining with PEACH2: an FPGA switching fabric for high performance computing", International Conference on Field-Programmable Technology (ICFPT2013), Demo paper, pp. 466-469, Dec. 2013. doi: http://doi.ieeecomputersociety.org/10.1109/FPT.2013.6718416
     
  23. Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, and Mitsuhisa Sato, "Interconnect for Tightly Coupled Accelerators Architecture," IEEE 21st Annual Sympsium on High-Performance Interconnects (HOT Interconnects 21), short paper, pp. 79-82, Aug. 2013. doi: http://doi.ieeecomputersociety.org/10.1109/HOTI.2013.15
     
  24. Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, and Mitsuhisa Sato, "Tightly Coupled Accelerators Architecture for Minimizing Communication Latency among Accelerators," The Third International Workshop on Accelerators and Hybrid Exascale Systems (AsHES2013) in conjunction with IEEE International Parallel and Distributed Processing Symposium (IPDPS2013), pp. 1030-1039, May. 2013. doi: http://doi.ieeecomputersociety.org/10.1109/IPDPSW.2013.226
     
  25. Tetsuya Odajima, Taisuke Boku, Toshihiro Hanawa, Jinpil Lee, and Mitsuhisa Sato, “GPU/CPU Work Sharing with Parallel Language XcalableMP-dev for Accelerated Computing", International Workshop on Parallel Programming Models and Systems Software for High-End Computing (P2S2), pp. 97-106, Sep. 2012. doi: http://doi.ieeecomputersociety.org/10.1109/ICPPW.2012.16
     
  26. Hajime Fujita, Yutaka Matsuno, Toshihiro Hanawa, Mitsuhisa Sato, Shinpei Kato, and Yutaka Ishikawa, "DS-Bench Toolset: Tools for Dependability Benchmarking with Simulation and Assurance," 42nd IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012), 8 pages, Jun. 2012. doi: http://doi.ieeecomputersociety.org/10.1109/DSN.2012.6263915
     
  27. Shin’ichi Miura, Toshihiro Hanawa, Taisuke Boku, and Mitsuhisa Sato, "XMCAPI: Inter-Core Communication Interface on Multi-chip Embedded Systems", International Symposium on Embedded and Pervasive Systems (EPS 2011), in IFIP 9th International Conference on Embedded and Ubiquitous Computing, pp. 397-402, Oct. 2011. doi:http://doi.ieeecomputersociety.org/10.1109/EUC.2011.78
     
  28. Toshihiro Hanawa, Taisuke Boku, Shin’ichi Miura, Mitsuhisa Sato, and Kazutami Arimoto, "PEARL and PEACH: A Novel PCI Express Direct Link and Its Implementation," The Seventh Workshop on High-Performance, Power-Aware Computing (HPPAC 2011) in 25th International Parallel and Distributed Processing Symposium (IPDPS 2011), pp. 866-874, May 2011. doi:http://doi.ieeecomputersociety.org/10.1109/IPDPS.2011.232
     
  29. Toshihiro Hanawa, Taisuke Boku, Shin'ichi Miura, Mitsuhisa Sato, and Kazutami Arimoto, "PEACH: A Communication SoC for PCI Express Direct Link," IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIV), 1 page (poster), Apr. 2011 (PDF), Best Feature Award.
     
  30. Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Katsushi Asahina, Kazutami Arimoto, Shin’ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato, "An 80Gb/s Dependable multicore Communication SoC with PCI Express I/F and Intelligent Interrupt Controller," IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips XIV), 3 pages (regular), Apr. 2011 (PDF). doi:http://doi.ieeecomputersociety.org/10.1109/COOLCHIPS.2011.5890920
     
  31. S. Otani, H. Kondo, I. Nonomura, A. Ikeya, M. Uemura, Y. Hayakawa, T. Oshita, S. Kaneko, K. Asahina, K. Arimoto, S. Miura, T. Hanawa, T. Boku, M. Sato, "An 80Gb/s Dependable Communication SoC with PCI Express I/F and 8 CPUs", International Solid-State Circuits Conference (ISSCC 2011), No. 15.2, pp. 266-267, Feb. 2011. (Presentation and Exhibition) doi:http://doi.ieeecomputersociety.org/10.1109/ISSCC.2011.5746312
     
  32. Toshihiro Hanawa, Taisuke Boku, Shin’ichi Miura, Mitsuhisa Sato, and Kazutami Arimoto, ''PEARL: Power-aware, Dependable, and High-Performance Communication Link Using PCI Express", IEEE/ACM International Conference on Green Computing and Communitations (GreenCom? 2010), pp. 284-291, Dec. 2010. doi:http://doi.ieeecomputersociety.org/10.1109/GreenCom-CPSCom.2010.115
     
  33. Toshihiro Hanawa, Hitoshi Koizumi, Takayuki Banzai, Mitsuhisa Sato, and Shin'ichi Miura, "Customizing Virtual Machine with Fault Injector by Integrating with SpecC Device Model for a software testing environment D-Cloud," the 16th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC '10), pp. 47-54, Dec. 2010. doi:http://doi.ieeecomputersociety.org/10.1109/PRDC.2010.37
     
  34. Toshihiro Hanawa, Taisuke Boku, Shin’ichi Miura, Mitsuhisa Sato, and Kazutami Arimoto, "Power-aware, Dependable, and High-Performance Communication Link Using PCI Express: PEARL," IEEE International Conference on Cluster Computing (Cluster 2010), poster, 4 pages, Sep. 2010. doi:http://doi.ieeecomputersociety.org/10.1109/CLUSTERWKSP.2010.5613094
     
  35. Takayuki Banzai, Hitoshi Koizumi, Ryo Kanbayashi, Takayuki Imada, Toshihiro Hanawa, and Mitsuhisa Sato, "D-Cloud: Design of a Software Testing Environment for Reliable Distributed Systems Using Cloud Computing Technology", the 2nd International Symposium on Cloud Computing (Cloud 2010) in conjunction with the 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing (CCGrid 2010), pp. 631-636, May 2010. doi: http://doi.ieeecomputersociety.org/10.1109/CCGRID.2010.72
     
  36. Toshihiro Hanawa, Takayuki Banzai, Hitoshi Koizumi, Ryo Kanbayashi, Takayuki Imada, and Mitsuhisa Sato, "Large-Scale Software Testing Environment Using Cloud Computing Technology for Dependable Parallel and Distributed Systems," the 2nd International Workshop on Software Testing in the Cloud (STITC 2010), co-located with the 3rd IEEE International Conference on Software Testing, Verification, and Validation (ICST 2010), pp. 428-433, Apr. 2010. doi: http://doi.ieeecomputersociety.org/10.1109/ICSTW.2010.59
     
  37. Taiga Yonemoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, and Mitsuhisa Sato, "Flexible Multi-link Ethernet Binding System for PC Clusters with Asymmetric Topology," The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS '09), pp.49-56, Dec. 2009. doi: http://doi.ieeecomputersociety.org/10.1109/ICPADS.2009.104
     
  38. Toshihiro Hanawa, Mitsuhisa Sato, Jinpil Lee, Takayuki Imada, Hideaki Kimura, and Taisuke Boku, "Evaluation of Multicore Processor for Embedded Systems by Parallel Benchmark Program using OpenMP," the 5th International Workshop on OpenMP (IWOMP 2009), Lecture Notes in Computer Science 5568, Springer, pp. 15-27, Jun. 2009. doi: http://dx.doi.org/10.1007/978-3-642-02303-3_2
     
  39. Shin'ichi Miura, Toshihiro Hanawa, Taiga Yonemoto, Taisuke Boku, Mitsuhisa Sato, "RI2N/DRV: Multi-link Ethernet for High-Bandwidth and Fault-Tolerant Network on PC Clusters," the 9th Workshop on Communication Architecture for Clusters (CAC 2009) in International Parallel and Distributed Processing Symposium (IPDPS 2009), pp.1-7, Apr. 2009. doi: http://doi.ieeecomputersociety.org/10.1109/IPDPS.2009.5160894
     
  40. Toshihiro Hanawa, Taisuke Boku, Shin'ichi Miura, Takayuki Okamoto, Mitsuhisa Sato, and Kazutami Arimoto, "Low-Power and High-Performance Communication Mechanism for Dependable Embedded Systems,'' International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA '08), pp. 67-73, Jan. 2008. doi: http://doi.ieeecomputersociety.org/10.1109/IWIA.2008.8
     
  41. Y. Ishikawa, H Fujita, T. Maeda, M. Matsuda, M. Sugaya, M. Sato, T. Hanawa, S. Miura, T. Boku, Y. Kinebuchi, L. Sun, T. Nakajima, J. Nakazawa, and H. Tokuda, "Towards an Open Dependable Operating System," Proc. of 12th IEEE International Symposium on Object / component / service-oriented Real-time distributed Computing (ISORC 2009), Invited, Mar. 2009. doi: http://doi.ieeecomputersociety.org/10.1109/ISORC.2009.55
     
  42. Shin'ichi Miura, Takayuki Okamoto, Taisuke Boku, Toshihiro Hanawa, Mitsuhisa Sato, "RI2N: High-bandwidth and fault-tolerant network with multi-link Ethernet for PC clusters," Proc. of IEEE International Conference on Cluster Computing (Cluster 2008), pp. 274-279, Sep.-Oct. 2008. doi:
     
  43. Toshihiro Hanawa, Yusuke Hirota, and Soichiro Ikuno, "Implementation of Variable Preconditioned GCR method with Mixed Precision on Cell BE," Proc. of the 13th Biennial IEEE Conference on Electromagnetic Field Computation (CEFC 2008), p. 247, May 2008. doi:
     
  44. Shin'ichi Miura, Taisuke Boku, Takayuki Okamoto, and Toshihiro Hanawa, "A dynamic routing control system for high-performance PC cluster with multi-path Ethernet connection," Proc. of Workshop on Communication Architecture for Clusters (CAC 2008) in IEEE International Symposium on Parallel and Distributed Processing (IPDPS 2008), pp. 1-8, Apr. 2008. doi:
     
  45. Soichiro Ikuno, Toshihiro Hanawa, Teruou Takayama, and Atsushi Kamitani, "Evaluation of Parallelized Meshless Approach - Application to Shielding Current Analysis in HTS -," Proc. of the The 16th Conference on the Computation of Electromagnetic Fields (Compumag 2007), pp. 645-646, Jun. 2007. doi:
     
  46. Toshihiro Hanawa, Soichiro Ikuno, and Atsushi Kamitani, "Investigations on Iterative Method with Mixed-Precision on Cell Broadband Engine," Proc. of the The 16th Conference on the Computation of Electromagnetic Fields (Compumag 2007), pp. 1083-1084, Jun. 2007. doi:
     
  47. Toshihiro Hanawa and Soichiro Ikuno, "Large Scale Simulation for Optical Propagation in 3-D Photonic Crystal using the FDTD Method with Parallel Processing," The Twelfth Biennial IEEE Conference on Electromagnetic Field Computation (CEFC 2006), p. 403, May 2006. doi:
     
  48. T. Hanawa and S. Ikuno, “Numerical Simulation of Electromagnetic Field by Parallelized 3-D AIBO-FDTD,” Proc. of the 19th International Conference on Numerical Simulation of Plasmas and 7th Asia Pacific Plasma Theory Conference, pp. 178–179, Jul. 2005.
     
  49. T. Hanawa, T. Minai, Y. Tanabe, and H. Amano, “Implementation of ISIS-SimpleScalar?,” Proc. of The 2005 International Conference on Parallel and Distributed Processing Tech- niques and Applications (PDPTA 2005), Vol.I, pp. 117–123, Jun. 2005.
     
  50. T. Hanawa, M. Kurosawa, and S. Ikuno, “Investigation on 3-D Implicit FDTD Method for Parallel Processing,” Proc. of The Eleventh Biennial IEEE Conference on Electromagnetic Field Computation (CEFC 2004), (1 page), Jun. 2004.
     
  51. T. Hanawa, S. Ikuno, and A. Kamitani, “Application of Parallelized Multigrid Method to Solution of MHD Equilibrium with MPI,” Proc. of the The 14th Conference on the Computation of Electromagnetic Fields (Compumag 2003), pp. P74631-1–2, Jul. 2003.
     
  52. Y. Tanabe, T. Midorikawa, D. Shiraishi, M. Shigeno, T. Hanawa and H. Amano, “Per- formance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mecha- nism,” Proc. of the 2003 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA 2003), Vol. 3, pp. 1148–1154, Jun. 2003.
     
  53. T. Midorikawa, D. Shiraishi, M. Shigeno, Y. Tanabe, T. Hanawa and H. Amano, “SNAIL- 2: a SSS-MIN connected multiprocessor with cache coherent mechanism,” Proc. of the third International Conference on Parallel and Distributed Computing Applications and Technologies (PDCAT 2002), pp. 17–24, Sep. 2002.
     
  54. S. Ikuno, T. Hanawa and A. Kamitani, “Application of Multigrid Method to Solution of MHD Equilibrium with Parallel Processing,” In Proc. of The Tenth Biennial IEEE Conference on Electromagnetic Field Computation (CEFC 2002), p. 187, Jun. 2002.
     
  55. T. Midorikawa, T. Kamei, T. Hanawa, and H. Amano, “The MINC chip: Multistage In- terconnection Network with Cache control mechanism chip,” In Proc. of the 3rd International Conference on ASIC (ASICON’98), pp. 249–252, Aug. 1998.
     
  56. T. Midorikawa, T. Kamei, T. Hanawa, and H. Amano, “The Multistage Interconnection Network with Cache control mechanism (MINC) chip,” In Proceedings on the Asia and South Pacific Design Automation Conference 1998 (ASP-DAC ’98), pp. 337–338, Feb. 1998.
     
  57. A. Funahashi, T. Hanawa, T. Kudoh, and H. Amano, “Adaptive routing on Recursive Diagonal Torus,” In Proceedings on the International Symposium on High Performance Computing (ISHPC '97), Lecture Notes in Computer Science, Vol. 1336, pp. 171–182, Nov. 1997.
     
  58. T. Hanawa, X. Zhu, T. Kamei, and H. Amano, “nD-MIN: Multistage Interconnection Net- work with Multi-dimensional Structure,” In Proceedings on the Tenth ISCA International Conference on Parallel and Distributed Computing Systems (PDCS '97), pp. 247–252, Oct. 1997.
     
  59. T. Hanawa, T. Fujiwara, and H. Amano, “Hot Spot Contention and Message Combining in the Simple Serial Synchronized Multistage Interconnection Network,” In Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing (SPDP '96), pp. 298–305, Oct. 1996.
     
  60. T. Hanawa, H. Yasukawa, K. Nishimura, and H. Amano, “MINC: Multistage Interconnec- tion Network with Cache control mechanism,” In Proceedings of the Ninth ISCA International Conference on Parallel and Distributed Computing Systems (PDCS '96), pp. 310–317, Sep. 1996.
     
  61. A. Funahashi, T. Hanawa, and H. Amano, “Fault tolerance of the MIN with multiple outlets”, In Proceedings of 1995 Pacific Rim International Symposium on Fault-Tolerant Systems (PRFTS '95), pp. 204–209, Dec. 1995.
     
  62. T. Hanawa, H. Amano, and Y. Fujikawa, “Multistage Interconnection Networks with multiple outlets,” In Proceedings of the 1994 International Conference on Parallel Processing (ICPP '94), Vol. 1, pp. 1–8, Aug 1994.
     
  63. H. Amano, T. Hanawa, M. Sasahara, and J. Terada, “Matrix calculations on a multiprocessor based on the SSS-multistage interconnection network,” In Proceedings of 10th Symposium on Advances in Numerical Methods for Large Sparse Sets of Linear Equations, Matrix Analysis and Parallel Computing (PCG ’94), pp. 20–29, Mar 1994.

Presentations (reviewed)

  1. Yuta Kuwahara, Toshihiro Hanawa, and Taisuke Boku, "A proposal of GMPI: GPU self MPI for GPU clusters," Annual Meeting on Advanced Computing System and Infrastructure (ACSI) 2016, Jan. 2016. [Outstanding Research Award]
     
  2. Toshihiro Hanawa, Taisuke Boku, "Tightly Coupled Accelerators with Proprietary Interconnect and Its Programming and Applications" (S5519), GPU Technology Conference, Mar. 2015.
     
  3. Kazuya Matsumoto, Toshihiro Hanawa, Yuetsu Kodama, Hisafumi Fujii, and Taisuke Boku, "Implementing CG Method on GPU Cluster with Proprietary Interconnect TCA for GPU Direct Communication", Annual Meeting on Advanced Computing System and Infrastructure (ACSI) 2015, Jan. 2015.
     
  4. Toshihiro Hanawa, "GPU Cluster with Proprietary Interconnect Utilizing GPU Direct Support for RDMA," GPU Technology Conference, Mar. 2014.

Posters

  1. Toshihiro Hanawa, Takahiro Kaneda, and Hideharu Amano, "Evaluation of Graph Application using Tightly Coupled Accelerators," International Supercomputing Conference (ISC'17) research poster, Jun. 2017.
     
  2. Hiroaki Umeda, Toshihiro Hanawa, Mitsuo Shoji, Taisuke Boku, and Yasuteru Shigeta, "Development of GPU-accelerated Fragment Molecular Orbital Program," Annual Meeting on Advanced Computing System and Infrastructure (ACSI) 2016, Jan. 2016.
     
  3. Hiroaki Umeda, Toshihiro Hanawa, Mitsuo Shoji, Taisuke Boku, Yasuteru Shigeta, "Large-scale MO Calculation with GPU-Accelerated FMO Program," SC15 poster, Nov. 2015. URL:http://sc15.supercomputing.org/sites/all/themes/SC15images/tech_poster/tech_poster_pages/post198.html
     
  4. Toshihiro Hanawa, Hisafumi Fujii, Kazuya Matsumoto, Yuetsu Kodama, Taisuke Boku, "Evaluation of FFT Code for GPU Cluster Using Tightly Coupled Accelerators Architecture," HPC in Asia Poster, in conjunction with International Supercomputing Conference (ISC'15), Jul. 2015.
     
  5. Hiroaki Umeda, Toshihiro Hanawa, Mitsuo Shoji, Taisuke Boku, Yasuteru Shigeta, "Development of GPU-accelerated FMO Program with OpenFMO and its Performance Benchmark," ICQC 2015 Satellite Symposium in Kobe "Novel computational methods for quantitative electronic structure calculations", poster session, Jun. 2015.
     
  6. Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato, "Tightly Coupled Accelerators Architecture for Low-latency Inter-Node Communication Between Accelerators," SC14 poster, Nov. 2014. URL: http://sc14.supercomputing.org/sites/all/themes/sc14/files/archive/tech_poster/tech_poster_pages/post249.html
     
  7. Toshihiro Hanawa, "Proprietary Interconnect with Low Latency for HA-PACS/TCA," HPC in Asia Poster, in conjunction with International Supercomputing Conference (ISC'14), Jun. 2014. [Best Poster Award]
     
  8. Hiroaki Umeda, Toshihiro Hanawa, Mitsuo Shoji, and Taisuke Boku, "GPU accelerated Fock matrix preparation routine in OpenFMO," 4th AICS symposium, Dec. 2013.
     
  9. Hisafumi Fujii, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato, "Evaluation of parallel GPU application using Tightly Coupled Accelerators," 4th AICS symposium, Dec. 2013.
     
  10. Tetsuya Odajima, Taisuke Boku, Mitsuhisa Sato, Toshihiro Hanawa, Yuetsu Kodama, Raymond Namyst, Samuel Thibault, Olivier Aumage, "Work Sharing with GPU and CPU on PGAS Programming Language XcalableMP-dev," 4th AICS symposium, Dec. 2013.
     
  11. Yuetsu Kodama, Taisuke Boku, Toshihiro Hanawa, Mitsuhisa Sato, "HA-PACS/TCA," 4th AICS symposium, Dec. 2013.
     
  12. Tetsuya Odajima, Taisuke Boku, Mitsuhisa Sato, Toshihiro Hanawa, Yuetsu Kodama, Raymond Namyst, Samuel Thibault, Olivier Aumage, "Task size control on high level programming for GPU/CPU work sharing," HPC in Asia Workshop, in conjunction with International Supercomputing Conference (ISC'13), Jun. 2013.
     
  13. Hiroaki Umeda, Toshihiro Hanawa, Mitsuo Shoji, and Taisuke Boku, “GPU accelerated Fock matrix preparation in OpenFMO,” HPC in Asia Workshop in conjunction with International Supercomputing Conference (ISC’13), Jun. 2013.
     
  14. Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato, "HA-PACS/TCA: Tightly Coupled Accelerators for Low-Latency Communication among GPUs", HPC in Asia Workshop, in conjunction with International Supercomputing Conference (ISC'13), Jun. 2013.
     
  15. Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Mitsuhisa Sato, "HA-PACS/TCA: Tightly Coupled Accelerators for Low-Latency Communication among GPUs", GPU Technology Conference 2013, Mar. 2013 . http://on-demand.gputechconf.com/gtc/2013/poster/pdf/P0255_Hanawa.pdf
     
  16. Sugako Otani, Hiroyuki Kondo, Kazutami Arimoto, Toshihiro Hanawa, Shin'ichi Miura, Hiroya Kaneko, Taisuke Boku, Mitsuhisa Sato, "PEACH: a Multicore Communication SoC with PCI Express", 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2012), Mar. 2012.

Invited Talks

  1. Toshihiro Hanawa, Oakforest-PACS: New System in Joint Center for Advanced HPC (JCAHPC) Towards Realizing Fastest Supercomputer in Japan, Intel Xeon Phi Processor Launch 2016, Bangalore, Sep. 2016.
     
  2. Toshihiro Hanawa, TCA and AC-CREST project, Keynote, Developing Next-gen HPC Architectures --- A Hardware Prototyping Workshop, in conjunction with International Supercomputing Conference (ISC'16), Frankfurt, Jul. 2016.
     

Research Exhibitions and informal presentations

  1. Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, and Taisuke Boku, "Task level pipelining with PEACH2: an FPGA switching fabric for high performance computing," the 2013 International Conference on Field-Programmable Technology (ICFPT 13), Demo Session, Dec. 2013.
     
  2. Y. Ishikawa, M. Sato, T. Hanawa, and H. Fujita, "DS-Bench/D-Cloud: Dependability Measurement and Evaluation Tool," Workshop "Close Look at DEOS" in Symposium "Towards Open Systems Dependability", Dec. 2010.
     
  3. Yutaka Ishikawa, Mitsuhisa Sato, Toshihiro Hanawa, Hajime Fujita, Takayuki Banzai, Hitoshi Koizumi, and Shin'ichi Miura, "Dependability Measurements and Evaluation Tool: DS-Bench/D-Cloud", The 16th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'10), Research Exhibition, Dec. 2010.
     
  4. T. Hanawa, M. Sato, R. Kanbayashi, T. Banzai, and H. Koizumi, “Large-scale Test Farm using Cloud-computing System,” Korea-Japan E-Science Joint Symposium, (Oral Presentation), Aug. 2009.

Books

  1. Taisuke Boku, Osamu Tatebe, Daisuke Takahashi, Kazuhiro Yabana, Yuta Hirokawa, Masayuki Umemura, Toshihiro Hanawa, Kengo Nakajima, Hiroshi Nakamura, Tsuyoshi Ichimura, Kohei Fujita, Yutaka Ishikawa, Mitsuhisa Sato, Balazs Gerofi, and Masamichi Takagi, "Oakforest-PACS," Contemporary High Performance Computing: From Petascale Toward Exascale, Jeffrey S. Vetter (Editor), CRC Computational Science Series, Vol. 3, 1st Ed., Taylor and Francis, ISBN 978-1138487079, Sep. 2018. (To be published)
     
  2. Taisuke Boku, Toshihiro Hanawa, Yoshinobu Kuramashi, Kohji Yoshikawa, Mitsuo Shoji, Yuetsu Kodama, Mitsuhisa Sato, and Masayuki Umemura, "HA-PACS: A Highly Accelerated Parallel Advanced System for Computational Sciences," Contemporary High Performance Computing: From Petascale Toward Exascale, Jeffrey S. Vetter (Editor), CRC Computational Science Series, Vol. 1, 1st Ed., Taylor and Francis, ISBN 978-1466568341, Apr. 2013.
     
  3. Toshihiro Hanawa, Mitsuhisa Sato, "D-Cloud: Software Testing Environment for Dependable Distributed Systems Using Cloud Computing Technology," Software Testing in the Cloud, Perspectives on an Emerging Discipline, Scott Tilley, Tauhida Parveen (Editors), IGI Global, ISBN 9781466625365, pp. 340-356, Nov. 2012.
     
  4. Toshihiro Hanawa, Hajime Fujita, "Dependability Test Support Tools," Open Systems Dependability -- Dependability Engineering for Ever-Changing Systems, Mario Tokoro (Editor), CRC Press, ISBN 978-1-4665-7751-0, pp.112-123, Nov. 2012.
     
  5. Mitsuhisa Sato, Toshihiro Hanawa, Matthias Mueller, Barbara Chapman, and Bronis R. de Supinski (Editors), "Beyond Loop Level Parallelism in OpenMP: Accelerators, Tasking and More," Lecture Notes in Computer Science, Programming and Software Engineering Vol. 6132, Springer Verlag, ISBN: 978-3-642-13216-2, Jun. 2010.

Reports

  1. SAPI Team, Special Assistance for Project Implementation(SAPI) for Malaysia Higher Education Loan Fund Project (II) Final Report, Japan Bank for International Cooperation (JBIC), Dec. 2001.

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Last-modified: 2018-06-17 (日) 00:48:50 (1140d)